Many serializer/deserializer (SERDES) implementations used for high-speed digital communications utilize a phase interpolator to generate an arbitrary clock phase. In order to generate the arbitrary clock phase, the phase interpolator typically requires a set of fixed clock phases as inputs. The set of fixed clock phases may be generated centrally, and subsequently shared among multiple communication lanes via global distribution. Alternatively, the set of clock fixed phases may be generated locally in each communication lane, close to the destination.
A centrally generated set of fixed clock phases amortizes power costs among the multiple communication lanes, but increases the global buffering power and phase error accumulation necessary to distribute the set of fixed clock phases. A locally generated set of fixed clock phases consumes less global buffering power, but the power cost of generating the set of fixed clock phases cannot be amortized. As such, the decision to generate the set of fixed clock phases centrally or locally balances power and performance considerations.